Many types of memory devices such as Dynamic Random Access Memory (DRAM) devices store information in memory cells arranged as an array of selectable rows and columns. Lines connecting each row are commonly referred to as word lines. Each column typically comprises two bit lines, each bit line connected to every other memory cell in the column. Data is read from the array by activating the word line containing the desired memory cell. Data stored by each memory cell coupled to the activated word line is transferred to sense amplifier circuitry via the bit lines for amplification. The column containing the desired memory cell is then activated, and the amplified data read out of the array onto a local data bus. The data is then read off chip.
A DRAM read operation occurs in several stages. At the beginning of a read operation, the sense amplifier circuitry is disabled and the bit lines are pre-charged to a matching intermediary voltage level. Bit line pre-charging is then disabled. Next, the storage capacitor of the desired memory cell is coupled to its bit line by activating the word line that actuates the memory cell's access transistor. The other bit lines in each column remain at their pre-charged level. Each selected storage capacitor shares charge with its bit line, slightly altering the pre-charged bit line voltage levels.
After a predetermined amount of time, referred to herein as the bit line signal development time, the sense amplifier circuitry is enabled. The bit line signal development time is the amount of time a storage capacitor should be coupled to a bit line before the sense amplifier circuitry is enabled. The sense amplifier circuitry amplifies the small voltage difference between the selected bit line and the adjacent bit line until one bit line is driven to a logic low level and the other bit line is driven to a logic high level. If the sense amplifier circuitry is too soon, the selected storage capacitor may not have sufficient time to charge its bit line to a voltage level sufficient for sensing. The desired column can be read after sensing is complete. The storage capacitor, which is still connected to the selected bit line because its word line remains active, is also driven to a full voltage level (refreshed) by the action of the sense amplifier circuitry.
Bit line signal development time is dominated by the RC delay of the longest bit line. As such, variation in transistor performance, e.g., as caused by transistor mismatches (i.e., p-fet devices that are stronger or weaker than their complimentary n-fet devices), has only a negligible affect at best on the time needed for bit line signal levels to sufficiently develop prior to sensing. However, operation of bit line sense amplifier circuitry is conventionally controlled by an enable signal generator that is highly sensitive to variation in transistor performance. Conventional enable signal generators activate an enable signal applied to bit line sense amplifier circuitry after a delay lapses during a read or refresh operation. While the delay is selected to provide sufficient bit line signal development time, the delay is a function of transistor performance. As such, the point at which bit line sense amplifier circuitry is enabled conventionally varies as a function of transistor performance, particularly in the enable signal generator.
One conventional enable signal generator includes a chain of inverters. Another conventional enable signal generator includes an inverter driven by a single constant-current source where the inverter output switches logic states some time after the constant-current source is coupled to the inverter input. In either case, the delay allocated to allow bit line signal levels to develop before sensing is a function of transistor performance. While the constant-current source implementation described above is less affected by transistor mismatches, the speed of the inverter output stage is nonetheless remains function of transistor matching. By some estimates, the time allocated for bit line signal level development can vary as high as 87% across a wide process window even though bit line signal development time is predominantly a function of RC delay. As such, bit line sensing operations in conventional memory devices become problematic when the devices contain transistors that are not well matched.